1. Purpose of the gate
The design software places, routes and times the benchmark designs on the new device, and the bitstreams it generates load and run correctly when the device model is simulated with them, so the software and the silicon agree before tape-out.
An FPGA without software is unusable, and software that disagrees with the silicon is worse. This gate checks, before tape-out, that the device model in the design software matches the device being taped out, and that what the software writes is what the silicon will do.
The core evidence is configured design simulation: benchmark and test designs are taken through the full software flow, their bitstreams are loaded into the device model in simulation, and the simulated device must behave as each design describes. Encrypted, authenticated and partial bitstreams are included. Each failure is traced to the silicon, the bitstream generator or the format.
The review also checks readiness for first silicon: the bring-up designs, the software build that will configure first parts and the reference designs for development kits. If the software is not ready when silicon arrives, bring-up waits.
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