1. Purpose of the gate
Every hard IP block has a source, a version and an integration specification, and its place in the device floorplan and its connection to the fabric, clocks and configuration logic are agreed.
This gate fixes what is built into the device beside the fabric and how it connects. After it, tile designers build the interface tiles around each block, the configuration team adds each block's settings to the bitstream format, verification plans the block connections and the software team describes each block to customers.
The review checks that every block has a source and a version, that its silicon status is known, and that its integration specification covers the fabric interface, clocks, resets, configuration settings, test access, power and the timing interface the software will model.
It also checks the floorplan. In a column-based fabric, hard blocks interrupt columns of logic, memory and arithmetic, and the routing must pass around them. A placement that is convenient for one block can make the whole fabric harder to route or the package harder to design.
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