1. Purpose and scope
No customer can use an FPGA without the vendor's design software. The software turns a customer's design into a bitstream: it synthesises the design, maps it onto look-up tables, registers, memories and arithmetic blocks, packs them into logic blocks, places them, routes every connection through the routing architecture, analyses timing and power, and writes the bitstream. For a new family, every one of those steps needs the new device described to it, and its quality decides what customers believe the silicon can do.
This stage adds the device to the production software: the device model and routing graph, packing and placement rules, the router's view of the switch patterns, the timing models built from tile timing views, power models, the hard IP configuration options, the bitstream generator against the frozen format, and the programming tools. It closes with the pre-silicon software readiness gate, where benchmark designs run through the full flow and the bitstreams the software writes load and run correctly in configured design simulation.
Timing data at this point is advance data, from simulation of the tiles and hard IP rather than measurement. The software must say so to its users, and it must be able to take preliminary and then production data from silicon later without customers' designs changing in ways they cannot see.
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