1. Purpose and scope
Physical design of an FPGA is assembly at scale. The tiles are already laid out; this stage arrays them into the fabric, places the hard blocks, builds the clock network and the power grid across the whole die, adds the configuration logic and the input and output ring, and closes the checks the foundry needs. It ends with tape-out of the first family member, the second technical readiness review of the lifecycle.
Timing closure has a different meaning here than on a fixed function chip. The paths a customer's design will use are not known, so the stage closes the fixed parts of the device, such as the configuration path, the clock network, the hard IP interfaces and the input and output timing, and checks that the assembled fabric matches the tile timing views the software uses. Power integrity is checked with high activity configurations that represent demanding customer designs, because the device must work for designs the vendor never sees.
The tape-out review also confirms what tape-out depends on: the process design kit versions used for sign-off, the silicon status of each hard IP block, the bring-up plan, the qualification plan and the first test configurations. Later family members repeat much of this stage with the same tiles and a new floorplan.
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