1. Purpose and scope
By the start of this stage the tiles and the device RTL are frozen and the verification environment is complete and running. The work now is results: running the regressions, closing the coverage the plan sets for every area of the device, and driving every bug found to a fix or a waiver. Design does not stop; it fixes what verification finds, under review, because every tile change repeats across the fabric.
Verifying an FPGA covers areas few other chips have: the configuration controller and its interfaces, the frame addressing of the configuration memory, partial reconfiguration, readback and upset detection, and the security features, including what the device does when authentication fails, when a key is missing or when tampering is detected. Failure and tamper responses are verified on purpose, not assumed from the normal path.
It also has a step few other chips need: configured design simulation. The device model is loaded with bitstreams generated by the vendor's own software from test designs, and the simulated device must behave as the design describes. This tests the fabric, the configuration logic and the bitstream generator together. It starts here and continues to the pre-silicon software readiness gate.
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