Before the Product RTL freeze gate: is the product RTL feature complete, with the IP integrated, the test architecture built in and the verification plan extended and mostly run? The program and tape-out manager confirms.
MustProduct RTL is feature complete against the frozen product specification, with the test chip blocks fixed from the silicon lessons.
MustEach lesson for product silicon is closed in the RTL, or carried as an accepted risk with an owner.
MustIP deliverables are final and integrated, with their versions recorded.
MustThe verification plan is extended to the full product scope and most of it is run, with the open items listed.
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