Confirms the design is complete and checked, and its verification environment ready, before the RTL freeze; coverage closure and verification sign-off follow on the frozen design in the next stage. The RTL design lead and the verification architect complete it.
MustAll planned features are implemented and reviewed.
MustLint and clock domain crossing results are clean or waived with reasons.
MustPower intent checks are clean against the power intent description.
SeeStandard: IEEE 1801
MustThe register map is generated from the design, matches the interface specification and is released to the software teams.
24 more items for registered members.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.