1. Purpose and scope
Implementation for an automotive chip follows the same broad flow as any SoC: synthesis, test insertion, floorplan, placement, clock tree, routing, timing closure and physical verification. What changes is the yardstick. The design must work for the whole of the mission profile, which describes the temperatures, supply conditions and operating hours the customer expects over the vehicle's life, at the corners of the temperature grade. Reliability sign-off therefore checks electromigration, self-heating, transistor ageing and related wear-out effects against that profile rather than against a consumer use case, and timing is closed with ageing taken into account.
Two safety needs reach into the layout. The dependent failure analysis requires redundant logic, such as lockstep cores or duplicated monitors, to be physically separated and fed by independent or monitored clocks and supplies so that one local defect cannot hit both copies. And the in-system tests the chip runs in the vehicle, logic and memory built-in self-test at start-up and during operation, must be inserted and timed so that they meet the latent fault detection the FMEDA assumed.
In scope: test insertion and pattern generation, physical implementation, separation of redundant logic, timing and physical sign-off at the temperature grade corners, reliability sign-off, the initial test program and the silicon validation plan, and tape-out. Out of scope: silicon bring-up and characterisation, which follow in Silicon Validation & Safety Mechanism Testing.
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