1. Purpose of the gate
Firmware, drivers, runtime and compiler run on silicon, the target workloads run end to end with correct results, and differences from the design are listed as errata.
This gate is the accelerator's equivalent of silicon validated, judged by software. It confirms that the full stack, firmware to compiler, runs the target workloads on silicon with correct results, that multi-chip links are stable, and that every difference from the design is recorded with a workaround or a fix plan.
Passing it lets benchmarking start in earnest and lets the product plan early access with known errata. It is also the point where the need for a further silicon revision becomes clear.
Correctness is judged against framework references, not only against the emulation runs, because some issues appear only at full size and speed.
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