1. Purpose of the gate
The design code is feature complete. From here only reviewed bug fixes are accepted.
RTL freeze stabilises the design so implementation can close timing and verification can close coverage. It also releases the register map to the software teams, so drivers and firmware are written against the real design.
Several decisions that shape implementation and test must be frozen here: power intent, DFT architecture, verification methodology, package technology and the PDK version.
For an accelerator, the compute array is often the most regular part of the design and the memory system and network the most irregular. Reviewers should look closely at the irregular parts, where late features and corner cases hide, and at the control logic that sequences work on the arrays.
RTL freeze is also when test strategy becomes real: scan, compression, memory self-test and test access must be in the design now, because adding them later disturbs timing closure and verification.
The review checks the health of the design as well as its completeness: how fast bugs are still arriving, which blocks change most often, and whether those blocks are on the critical path for implementation.
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