1. Purpose and scope
This stage writes the design code from the microarchitecture and verifies it. Accelerators bring particular demands: large regular arrays that must be correct at every edge case of data type and rounding, memory systems whose performance matters as much as their correctness, and a software interface that real software must be able to use.
One gate closes the stage. RTL freeze marks the design as feature complete, after which only reviewed fixes are accepted. Design and verification climb together: the verification environment, with its bit exact references, checkers, coverage model and the emulation platform, is built here alongside the design code, so that the results can be closed on the frozen design. Verification sign-off follows in the next stage, on that frozen design: it confirms that coverage goals are met, that performance verification agrees with the model, and that every open bug is fixed or waived, while the software stack starts running real workloads on emulation.
12 more sections for registered members.