Training plan · Builders

Building with chips: from device choice to a product people can use

Makers, engineers, students and small teams who build things with the industry's parts: boards with microcontrollers and FPGAs, firmware, open hardware, tools and, sometimes, a first small chip on a shared wafer run. The plan follows the FPGA, firmware and startup lifecycles to show what professional teams check at each step, from choosing a device and a toolchain to bring-up, security, compliance and keeping a product in production. It suits any level of experience; each module starts from the basics and points to the checklists teams use.

10 modules across three levels, a capstone and collateral. Built on the Hub's lifecycles, stage guides, gate packs, checklists, tool flows, decisions and governance flows. Version 0.1.0, revised 2026-10-19.

By the end you can

Explain the stages of the FPGA and firmware lifecycles and where a board, a design and software meet.
Choose a device, package and toolchain for a project and record why.
Find open tools, reading paths and people working on the same parts.
Run design reviews for clock domain crossings and timing closure on an FPGA design.
Plan and run a board bring-up with the hand-offs between hardware, logic and firmware.
Design a boot and update scheme that can recover from a bad update.
List the security basics for a connected device, from protected configuration to signing keys.
Prepare a small design for a shared wafer run and plan how the samples will be tested.
Prepare a product for compliance testing and a release.
Plan production test, second source and obsolescence for a product that will be built in numbers.

The plan at a glance

Foundation

The lifecycles builders work in, choosing a device and toolchain, and open tools and reading.

The lifecycles a builder works in (small)
Choosing a device, package and toolchain (medium)
Open tools, reading paths and people (small)

Practitioner

FPGA design and timing, board bring-up, firmware and boot, security basics and a first chip on a shuttle.

FPGA design, verification and timing closure (large)
Board design and bring-up (large)
Firmware, boot and safe updates (medium)
Security basics for a connected device (medium)
A first chip on a shared wafer run (large)

Advanced

Compliance and release, and production, second source and obsolescence.

Compliance testing and release (medium)
Production, second source and obsolescence (medium)

Capstone: Take one project from device choice to a release.

Register or sign in to read a sample module

The sample module is for registered members; the full plan, its exercises, self-checks and collateral are part of paid plans. Registration is free and takes a minute. You come back to this page afterwards.

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