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Cordoba, Argentina · Listed on the Hub · Posted by the company · Listed until
Design top-level simulation and FPGA tests from the test plan to ensure correct system-level integration before tape-out
Collaborate with digital design engineers to integrate software with SoC-specific accelerators, so firmware is ready for silicon bring-up on day 1
Profile and map neural-network models onto hardware accelerators when required, translating high-level framework metrics into efficient machine code and data flow
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