Jobs / Principal Design Verification Engineer- SerDes/PHY IP
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Principal Design Verification Engineer- SerDes/PHY IP
Astera LabsVerificationStaff / PrincipalOn-site
San Jose, United States · Listed on the Hub · Posted by the company · Listed until
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP - the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.
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