Before a single line of RTL gets written, a chip program spends weeks to months turning a committed product plan into something an engineering team can actually build against. That's what happens in the Specification & Architecture stage, and it's where most of a program's later schedule risk either gets designed out or quietly baked in.
This stage's job is to leave behind a small set of concrete artifacts: an architecture specification describing the major blocks and how they connect, a micro-architecture specification detailed enough for RTL designers to start coding against, defined interfaces between blocks, and a documented feasibility study showing the approach can actually hit its power, performance, and area targets. Nothing downstream, including RTL, verification, and physical design, has a stable target to aim at until these exist.
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