Tool · Verification & Validation
Verilator
An open-source tool that translates synthesisable SystemVerilog into optimised C++ or SystemC models, giving very fast cycle-based simulation. It has become standard in RISC-V, academic and continuous-integration flows where licence cost or speed dominates.
- Type
- Tool
- Domain
- Verification & Validation, Simulation
Notes
It supports only a synthesisable subset and limited four-state modelling, so it complements rather than replaces a full simulator.
Related terms
- Cycle-based simulation
- RTL simulation
- SystemC
- ISS
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Tools
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