Process · Verification & Validation
UVM phases
The ordered set of simulation stages that every UVM component executes, including build, connect, end_of_elaboration, run and the report and final phases. Build runs top-down and connect bottom-up, which is what lets hierarchies assemble themselves.
- Also known as
- uvm_phase, Phasing
- Type
- Process
- Domain
- Verification & Validation, UVM
Notes
The run phase is the only time-consuming one; the twelve runtime subphases such as reset and configure are optional.
Related terms
- UVM environment
- UVM objection
- UVM factory
- UVM test
Part of the Verification & Validation glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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