Artefact · Design & Architecture
Design kit (structured ASIC)
The package a structured ASIC vendor gives customers to design onto a base array: the cells and pre-built blocks, timing and power models, the rules for the custom layers, and a reference design flow.
- Also known as
- Structured ASIC design kit
- Type
- Artefact
- Domain
- Design & Architecture, Structured ASIC
Overview
A structured ASIC design kit is what a customer team uses to turn its design into custom layers for a particular base array. It plays the same part a process design kit plays for a standard cell chip, but it describes the vendor's base array and its pre-built resources rather than the bare process.
How it works
The kit describes the base array: the logic cells or tiles, the memories, the clocks, the input and output cells and any hard blocks, with their positions and how they can be connected. It provides timing, power and signal integrity models for these resources and for routing in the custom layers. It sets the rules for those layers, and it supplies a reference flow, scripts and checks that take a netlist through placement, routing, timing closure and sign-off.
Kits are versioned and released by the vendor. Customer designs record the kit version they used, and the vendor checks submitted designs against it before tape-out. A change to the base array or its models is issued as a new kit version.
The kit sits on top of the foundry's process design kit, which the vendor uses to design and qualify the base array itself.
Examples
- A kit with tile models, memory timing, custom via rules and a reference place and route flow.
- A new kit version issued after the base array's timing models were updated from silicon data.
- A customer design checked by the vendor against the kit version recorded with it.
- A conversion team using the kit to map an FPGA design onto the base array.
Why it matters
The kit is what makes the vendor's pre-built base usable by customers, and what makes their results predictable. A complete, correct kit means timing and power on silicon match what the customer saw in design. Structured ASIC vendors' library and flow teams build it, and customer design engineers use it.
In the structured ASIC lifecycle, the kit is released after the base array is designed and characterised, and it is the main input to customer design intake and implementation.
It matters most to: ASIC Design Engineer (Structured and Custom Digital), FPGA-to-ASIC Conversion Engineer, Release Manager, Silicon and Design Kits
Common confusions
- Not the same as a process design kit (PDK)
- A PDK comes from the foundry and describes a process for designing any chip on it. A structured ASIC design kit comes from the structured ASIC vendor and describes one base array and its custom layers.
- Not the same as an FPGA vendor's design software
- FPGA software generates a bitstream to load into a finished device. A structured ASIC design kit produces mask layouts for layers still to be made.
Sources
- A Methodology for FPGA to Structured-ASIC Synthesis and Verification (DATE 2006) (opens in a new tab), Design, Automation and Test in Europe (DATE) proceedings archive, 2026-11-10
- Structured ASIC platform (opens in a new tab), Wikipedia, 2026-11-10
- Process design kit (opens in a new tab), Wikipedia, 2026-11-10
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
Where it appears on the Hub
Used on 3 pages of the Hub. In each group, the pages that mention it most come first.
Suggest an improvement
Suggest an improvement to this entry
A clearer definition, an example, a correction or a source an editor can check. Editors review every suggestion before the entry changes.
Last reviewed . Written by The Semiconductor Hub editorial team. The full glossary