Acronym · Design & Architecture
LLC (Last Level Cache)
The largest and slowest cache level on a chip, shared by multiple cores or agents, and the final filter before requests go to main memory or to a system-level interconnect.
- Also known as
- L3 cache, System level cache, SLC
- Type
- Acronym
- Domain
- Design & Architecture, Memory and cache
Notes
Whether it is inclusive, exclusive or non-inclusive of the levels above changes both effective capacity and coherency complexity.
Related terms
Part of the Design & Architecture glossary, with every term in the topic and the lifecycles, tools and standards that use them.
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