Gate array

Overview

A gate array is a semi-custom chip made from wafers that already carry a regular array of transistors, processed up to the point where they are wired together. Each customer design is created by adding its own metal interconnect layers on top. Because only those layers are custom, a gate array is cheaper and quicker to make than a fully custom chip, though it uses silicon less efficiently.

How it works

The vendor designs and makes base wafers with rows of identical transistors or simple gates, plus input and output cells around the edge. The wafers are processed up to the lower layers and stored.

A customer design is described as a netlist of logic. The vendor's tools map it onto the array, placing each function on a group of transistors and routing the connections. Only the masks for the custom metal and contact layers are made, and the stored wafers are finished with them.

In early gate arrays, routing ran in channels between the rows. Later sea-of-gates arrays covered the die with transistors and routed over unused ones. Structured ASICs went further by also pre-building clocks, memories and much of the routing in the base.

Examples

• A mask-programmed array of logic gates, wired in metal for each customer.
• A sea-of-gates array where routing runs over unused transistors.
• An older industrial product still made on a gate array whose base wafers are kept in a wafer bank.
• A design moved from an old gate array to a structured ASIC when the gate array process was retired.

Why it matters

Gate arrays made custom logic affordable for many companies before standard cell design and FPGAs were common, and they are the direct ancestor of today's structured ASICs. Understanding them explains why a structured ASIC shares a base and customises only a few layers. ASIC designers and structured ASIC teams meet the term in the history of the field and in older products still in service.

In the structured ASIC lifecycle, the gate array is the comparison point: the structured ASIC keeps its idea of a shared base and adds more pre-built content.

It matters most to: ASIC Design Engineer (Structured and Custom Digital), ASIC Vendor Engineering Manager

Common confusions

Not the same as a structured ASIC

Both share a pre-made base customised in a few layers. A structured ASIC also pre-builds clocks, memories, input and output cells and much of the routing, so fewer layers are custom and timing is more predictable.

Not the same as an FPGA

An FPGA is programmed after manufacture and can be changed. A gate array is fixed when its metal layers are made.

Sources

1. 1967: Application Specific Integrated Circuits employ Computer-Aided Design (The Silicon Engine) (opens in a new tab), Computer History Museum, 2026-11-10
2. Gate array (opens in a new tab), Wikipedia, 2026-11-10

Related terms

• Structured ASIC
• Base array
• ASIC

Where it appears on the Hub

No other page of the Hub uses this term yet.