DMA (Direct Memory Access)

Notes

Non-coherent DMA requires explicit cache maintenance in software, a perennial source of intermittent data corruption bugs.

Overview

DMA, short for direct memory access, is a way for hardware to move data between memory and peripherals, or between two areas of memory, without the processor copying each word itself. The processor sets up a transfer, a DMA engine carries it out, and an interrupt reports when it is done, leaving the processor free for other work. Most SoCs and microcontrollers include DMA, because without it fast peripherals such as network, storage, audio and camera interfaces would tie up the processor.

How it works

There are two broad styles. In third-party DMA, a DMA controller with several channels moves data on behalf of peripherals, which signal that they are ready over request lines. In bus mastering, the peripheral itself, such as a network controller or SSD, reads and writes memory directly. A controller channel is programmed with source and destination addresses, transfer width, burst size and length, and whether each address increments; memory addresses usually do, while a device's data register usually stays fixed. Transfers can run memory to memory, memory to device or device to memory.

Scatter-gather lets one operation collect data from many separate buffers, using a table or linked list of descriptors that the engine walks through. Cyclic transfers loop back to the start of the list, which suits ring buffers for audio. Completion is reported by interrupt or callback, and the Linux DMA engine guide advises starting the next transfer from the interrupt handler so the channel does not sit idle.

The hard part is keeping memory views consistent. If a processor cache holds a copy of a DMA buffer, the device may read stale data, or the processor may miss what the device wrote. Coherent systems handle this in hardware by snooping; others need software to clean and invalidate cache lines, which is why Linux separates coherent mappings from streaming mappings. Devices may also use bus addresses that differ from physical addresses, and an IOMMU can translate them and limit which memory each device can reach.

Examples

• A microcontroller filling a buffer from its ADC through a DMA channel while the processor sleeps, waking only on the completion interrupt.
• An audio interface fed by a cyclic DMA transfer that loops over a ring buffer so playback never waits for software.
• A network controller writing received packets into memory as a bus master, using a descriptor ring shared with its driver.
• An IOMMU on a server SoC restricting each PCIe device to the memory regions mapped for it.

Why it matters

SoC architects size DMA engines and interconnect bandwidth, RTL designers build DMA controllers and bus-master interfaces, and driver and firmware engineers program them. The throughput and power of most data-heavy subsystems depend on DMA, and mistakes in buffer mapping or cache maintenance are a common source of hard-to-find data corruption.

In the chip lifecycle, DMA capability and coherency are set at architecture, controllers and bus masters are verified in simulation and emulation with realistic traffic, drivers are developed on virtual platforms and brought up after first silicon, and DMA throughput is checked during post-silicon validation.

It matters most to: Cache Coherency Architect, Interconnect / NoC Architect, Linux Kernel Engineer, Peripheral and Bus IP Design Engineer, SoC Architect

Common confusions

Not the same as memory-mapped I/O

With memory-mapped I/O the processor itself reads and writes device registers at ordinary addresses. DMA is used to move the bulk data, so the processor only writes a few registers to start a transfer.

Not the same as RDMA

Remote direct memory access moves data between the memories of two computers over a network. Ordinary DMA works within one system. DMA vs RDMA

Not the same as cache coherency

DMA moves data; coherency is about keeping caches consistent with what was moved. Every DMA design has to decide whether hardware or software keeps the two in step.

Sources

1. Dynamic DMA mapping Guide (opens in a new tab), The Linux Kernel documentation (kernel.org), 2026-10-22
2. DMAengine controller documentation (opens in a new tab), The Linux Kernel documentation (kernel.org), 2026-10-22
3. Direct memory access (Wikipedia) (opens in a new tab), Wikimedia Foundation, 2026-10-22

Related terms

• AXI
• Accelerator
• Cache coherency
• Interrupt controller

Where it appears on the Hub

Used on 19 pages of the Hub. In each group, the pages that mention it most come first.