DFE (Decision Feedback Equaliser)

Notes

The first tap must settle within one unit interval, which is why very high rate links use loop unrolling or speculative DFE.

Overview

A DFE, or decision feedback equaliser, is a receiver circuit in a high-speed serial link that removes the interference left on the current bit by bits already received, using its own earlier decisions to work out how much to subtract. Because it feeds back clean decisions rather than filtering the noisy input, it cancels this intersymbol interference without boosting noise or crosstalk the way a linear equaliser does. Most SerDes receivers combine a DFE with linear equalisers such as a CTLE and FFE.

How it works

When a pulse travels down a lossy channel it spreads out, so part of each bit's energy lands on the following bits, known as post-cursor intersymbol interference. The DFE keeps a short history of the bits it has just decided. Each history bit is multiplied by a weight, or tap, that estimates how much that earlier bit leaks into the current one, and the sum is subtracted from the incoming signal just before the slicer makes its next decision. The first tap corrects the bit immediately before, the second the one before that, and so on. Tap weights are usually adapted automatically during link training and then tracked during operation.

The DFE's strengths come with limits. It is non-linear and can cancel only post-cursor interference, so pre-cursor effects must be handled by transmitter emphasis or a feed-forward equaliser. If a decision is wrong, the wrong correction is applied to the following bits, so errors can propagate in short bursts. The feedback loop must also settle within one bit time, which makes the first tap a critical timing path at high data rates and complicates clock and data recovery.

Each extra tap also adds circuitry and power, so tap count is a key trade-off. At the highest PAM4 rates, many receivers instead digitise the signal with an ADC and carry out equalisation in a DSP, an approach that scales better with process technology.

Examples

• A long-reach backplane SerDes receiver using a multi-tap DFE after a CTLE to recover data from a high-loss channel.
• A 224G SerDes design adding more FFE and DFE taps to offset the extra loss at its higher Nyquist frequency.
• A DDR5 PHY that includes receiver decision feedback equalisation on its data inputs.

Why it matters

A DFE often decides whether a long or lossy channel can run at the target rate without errors, so SerDes analogue and digital designers, signal integrity engineers and validation teams all work with its tap counts, adaptation and limits. Because each tap costs area and power, the DFE is one of the main levers in trading link reach against SerDes power.

In the chip lifecycle, DFE architecture and tap count are chosen during SerDes design, modelled in IBIS-AMI for system simulation, verified against channel models before tapeout, and tuned during post-silicon validation and link training in the field.

It matters most to: DDR PHY and Memory Interface Analog Designer, High-Speed Channel Design Engineer, SerDes Analog Front-End Designer, SerDes and High-Speed I/O Validation Engineer, SerDes Digital Design Engineer

Common confusions

Not the same as CTLE

A continuous-time linear equaliser is an analogue filter that boosts high frequencies to undo channel loss, amplifying high-frequency noise and crosstalk along with the signal. A DFE avoids that, but works only on post-cursor interference.

Not the same as FFE

A feed-forward equaliser is a linear filter on the incoming samples or transmitted symbols. It can address pre-cursor interference, which a DFE cannot.

Not the same as forward error correction

Forward error correction adds redundant bits so that errors can be corrected after the receiver has made its decisions. A DFE works before the decision, cleaning up the signal so fewer errors occur.

Sources

1. Overview of SERDES channel equalization techniques for serial interfaces (white paper) (opens in a new tab), Siemens Digital Industries Software, 2026-10-22
2. Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches (Madhumita Sanyal, Synopsys, 20 July 2023) (opens in a new tab), Semiconductor Engineering, 2026-10-22
3. Re-Architecting SerDes (Brian Bailey, 10 December 2020) (opens in a new tab), Semiconductor Engineering, 2026-10-22
4. DDR5/4 PHY IP (opens in a new tab), Synopsys, 2026-10-22

Related terms

• CTLE
• FFE
• DFE error propagation
• ISI

Where it appears on the Hub

Used on 7 pages of the Hub. In each group, the pages that mention it most come first.