Glossary comparison
LEC vs LVS: what is the difference?
The difference
Layout versus schematic checks that the drawn transistors and wiring match the netlist. LEC checks that two descriptions compute the same logic.
Logic equivalence checking compares RTL with a gate-level netlist. LVS compares a layout with a netlist at device level.
The two terms
LEC
Formal proof that two netlists, typically RTL against synthesised gates or pre- against post-ECO, implement identical combinational functions between matched state points.
LVS
Physical verification that extracts a netlist from the drawn layout and compares its devices and connectivity against the reference schematic or CDL netlist. It proves the layout implements the intended circuit before masks are made.
Side by side
| Field | LEC | LVS |
|---|---|---|
| Stands for | Logic Equivalence Checking | Layout Versus Schematic |
| Type | Acronym | Acronym |
| Domain | Verification & Validation | EDA Tools & Flows |
| Group | Formal verification | Physical verification |