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Tier 2: established / regionalSymposium / WorkshopTest & Reliability
Usual timing
Normally held in April/May. No confirmed next-edition date yet.
Organizer
IEEE Computer Society Test Technology Technical Council
Cadence
Annual
Usual host
Rotating, California, United States
Venue
—
Format
In-person
Scale
<500
Audience
VLSI test researchers and DFT practitioners
Notes
North American symposium on VLSI test technology, design-for-test and silicon debug.
From The Semiconductor Hub's Global Semiconductor Events Directory: a research seed, not yet editorially verified row by row. Spotted an error?Let us know.