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Tier 1: global flagshipVendor / User GroupEDA & Verification
Usual timing
Normally held in September/October. No confirmed next-edition date yet.
Organizer
TSMC
Cadence
Annual
Usual host
Santa Clara, California, United States
Venue
Santa Clara Convention Center
Format
In-person
Scale
500-2,000
Audience
EDA vendors, IP providers and TSMC design customers
Notes
TSMC's ecosystem forum where EDA and IP partners present certified flows and IP for TSMC process nodes.
From The Semiconductor Hub's Global Semiconductor Events Directory: a research seed, not yet editorially verified row by row. Spotted an error?Let us know.