This thread is for discussing the lifecycle document "Interface ASIC tape-out: gate review pack".
The review that releases the interface ASIC to the foundry after co-simulation with the transducer model across corners, with its trim architecture and register map fixed and its interface conformance planned. It is for ASIC design, verification, calibration, firmware and compliance engineers.
Read the document: https://www.thesemiconhub.com/lifecycle/mems/gates/mems-asic-tapeout/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.