This thread is for discussing the lifecycle document "Larger wafer equivalence shown: gate review pack".
The review at which devices built on the larger wafer are shown to match those on the original wafer within agreed limits, from substrate and epitaxy quality through parametrics to reliability, so qualification can be read across or repeated as planned. It closes Wafer Size Transition. This pack is for transfer, materials, characterisation, yield, reliability and quality leads.
Read the document: https://www.thesemiconhub.com/lifecycle/power-compound/gates/pwr-wafer-equivalence/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.