This thread is for discussing the lifecycle document "Device design freeze: gate review pack".
The review at which the cell structure, drift layer, edge termination, gate design and layout are fixed and the masks can be ordered. It closes Device Design & Simulation. This pack is for device design, TCAD, process, reliability, applications and packaging leads.
Read the document: https://www.thesemiconhub.com/lifecycle/power-compound/gates/pwr-device-design-freeze/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.