This thread is for discussing the lifecycle document "Density & Generation Roadmap: stage guide".
How a memory maker decides which DRAM, NAND and HBM generations, densities and interface standards to build next, and approves one generation for definition. It covers demand and bit cost modelling, tracking of JEDEC standards, system studies with platform makers and the generation business case. It is written for product line managers, memory systems architects, pricing and planning analysts and the engineering leads who frame the generation.
Read the document: https://www.thesemiconhub.com/lifecycle/memory/mem-roadmap/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.