This thread is for discussing the lifecycle document "Yield baseline established: gate review pack".
The review pack for yield baseline established in the test program and ATE development lifecycle: who takes part, the entry criteria and evidence, the agenda, the possible outcomes and the questions reviewers ask. For the gate chair, the presenters and the reviewers.
Read the document: https://www.thesemiconhub.com/lifecycle/test-program/gates/tp-yield-baseline/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.