This thread is for discussing the lifecycle document "Verification decks validated on test layouts: gate review pack".
The review at which every coded rule in the design rule check, layout versus schematic, antenna, density and electrical rule decks is shown to give the expected result on layouts written to pass and to fail it, in each supported tool category. It closes Physical Verification Decks. It is for physical verification and deck QA engineers, the rule manual owner, tool flow engineers and the layout and design teams who will sign off on the decks.
Read the document: https://www.thesemiconhub.com/lifecycle/pdk/gates/pdk-decks-validated/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.