This thread is for discussing the lifecycle document "Early access PDK release: gate review pack".
The review at which the first design kit, with target device models and draft design rules, is released to internal teams and selected partners for design studies and early IP planning. Its limits must be stated plainly. It is for design kit developers, release managers, device modellers, co-optimisation engineers and the customer enablement team.
Read the document: https://www.thesemiconhub.com/lifecycle/process-node/gates/process-node-pdk-early-access/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.