This thread is for discussing the lifecycle document "Wafer Sort & Known-Good Die: stage guide".
How each die is tested on the wafer to known-good-die quality before assembly, and how a bank of tested dies is built and managed. Written for known-good-die test engineers, wafer sort engineers, DFT engineers, die bank managers and the die suppliers who deliver tested dies.
Read the document: https://www.thesemiconhub.com/lifecycle/chiplet/chiplet-kgd/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.