This thread is for discussing the lifecycle document "Schematic & Circuit Design: stage guide".
How the circuit is designed and sized at transistor level, simulated against the frozen specification at nominal conditions and the main corners, and made ready for the Schematic design review. For analog, mixed-signal and RF designers, their leads, and the verification and layout engineers who start from the schematics.
Read the document: https://www.thesemiconhub.com/lifecycle/ams/ams-circuit-design/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.