This thread is for discussing the lifecycle document "Engineering samples: gate review pack".
This pack prepares the gate where early parts are released to lead customers for evaluation and design-in, with known issues documented. It covers errata disclosure, sample quantities, customer support material, the agenda and the decision record. It is for product managers, applications engineers, validation and quality leads.
Read the document: https://www.thesemiconhub.com/lifecycle/soc/gates/engineering-samples/document
Point out anything that is wrong, unclear or missing, and say which section you mean. Reviewers read this thread when they audit the document.